1. Technical Field
Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, embodiments of the present invention relate to a metal oxide semiconductor (MOS) transistor having a gate electrode including metal, and a method of manufacturing the MOS transistor.
2. Description of the Related Art
It is desirable for a gate insulation layer pattern in a conventional metal oxide semiconductor (MOS) transistor to have a thin equivalent oxide thickness (EOT) and to sufficiently reduce a leakage current between a gate conductive layer pattern and a channel region of the MOS transistor. Accordingly, the gate insulation layer pattern is usually formed using a material having a high dielectric constant.
When a gate conductive layer pattern including doped polysilicon is formed on the gate insulation layer pattern of the material having the high dielectric constant, a Fermi-level pinning effect may often occur so that mobilities of impurities doped in source/drain regions of the MOS transistor may be deteriorated. Thus, a flat band voltage (Vfb) of the MOS transistor, which is in proportion to a threshold voltage of the MOS transistor, may not be controllable within a desirable range.
In an effort to remedy the above-mentioned problem, metal has been used for a gate conductive layer pattern so as to reduce the Fermi-level pinning effect of the MOS transistor. When the gate conductive layer pattern includes metal, an increase of the EOT of the gate insulation layer pattern may be minimized by suppressing a poly depletion effect generated in the gate conductive layer pattern of doped polysilicon. Hence, a conventional gate structure in a MOS transistor generally includes a gate insulation layer pattern of high dielectric material and a gate conductive layer pattern of metal. Particularly, the gate conductive layer pattern usually includes a lower metal film adjusting a work function thereof, and an upper metal film serving as a wiring line for the MOS transistor.
As for the lower metal film of the gate conductive layer pattern, the work function of the gate conductive layer may vary in accordance with a type of the MOS transistor so as to properly adjust a threshold voltage of the MOS transistor. When the MOS transistor is an N type MOS (NMOS) transistor, the gate conductive layer pattern may have a work function of about 4.0 eV to about 4.3 eV. Meanwhile, the gate conductive layer pattern may have a work function of about 4.7 eV to about 5.0 eV when the MOS transistor is a P type MOS (PMOS) transistor.
In a formation of the MOS transistor, source/drain regions are formed by doping impurities into portions of a semiconductor substrate and by performing a thermal treatment process for activating the impurities doped into the semiconductor substrate. The thermal treatment process is usually performed at a temperature above about 1,000° C.
In the thermal treatment, however, the work function of the gate conductive layer pattern may be undesirably changed, deteriorating the electrical characteristics of the MOS transistor. For example, the work functions of the gate conductive layer pattern in the NMOS transistor may be changed from a range of about 4.0 eV to 4.3 eV into about 4.5 eV after the thermal treatment process. Additionally, the work function of the gate conductive layer pattern in the PMOS transistor may also be changed from a range of about 4.7 eV to 5.0 eV into about 4.5 eV. Such variations in the work functions of the gate conductive layer patterns may be caused by a reaction of the lower metal film relative to the upper metal film.
When the work function of the gate conductive layer pattern in the MOS transistor is changed to an undesired value, a threshold voltage of the MOS transistor may not be properly controlled. However, the thermal treatment process for activating the impurities is necessary for forming the source/drain regions so that this thermal treatment process may not be omitted from manufacturing processes of the MOS transistor. The present invention addresses these and other disadvantages of the conventional art.